1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to means for compensating a defunct memory cell.
2. Description of the Related Art
FIGS. 1 and 2 are circuit diagrams showing configurations of conventional semiconductor memory devices.
Some semiconductor memory devices have plural varieties with different input-output data widths, although they have the same capacity. For example, in 16-Mbit DRAMs, 4M.times.4-bit, 2M.times.8-bit, 1M.times.16-bit types etc., exist. FIGS. 1 and 2 show the cases of DRAMs whose input-output data widths are 4 bit and 8 bit respectively, although they have the same memory cell array structure.
In the DRAM shown in FIG. 1 having the 4-bit configuration, memory cell arrays ARRAY0 and ARRAY1 (hereinafter called ARRAY0 and ARRAY1 respectively) share groups of local IO lines IO00 to IO30 and IO01 to IO31, each of which is composed of 4 lines. Four respective sense amplifiers are connected to each of row decoders YDEC00 to YDECn0 and YDEC01 to YDECn1. These four sense amplifiers are also connected to each of four IO lines IO00 to IO30 and IO01 to IO31 (hereinafter called IO00 to IO31), respectively.
Upon reading and writing data, one of row decoders YDEC00 to YDECn0 and YDEC01 to YDECn1 is selected. Which one of row decoders YDEC00 to YDECn0 and YDEC01 to YDECn1 is selected and activated depends on an address signal input externally. No matter which row decoder is activated, one of data amplifier groups DA00 to DA30 and DA-01 to DA31 (hereinafter called DA00 to DA 31) which is connected to the memory cell array including the activated row decoder (hereinafter called YDEC) is activated while the other is not. In this manner, 4-bit data in total are input and output between ARRAY0 or ARRAY1 whichever including the selected memory cell and input-output terminals DQ1 to DQ4 via global internal input-output lines RWB1 to RWB4 (hereinafter called RWB1 to RWB4).
In the 8-bit configuration DRAM shown in FIG. 2, sense amplifiers of ARRAY0 and ARRAY1 share local IO lines IO00 to IO30 and IO01 to IO31 composed of 4 lines respectively, as in the 4-bit configuration DRAM shown in FIG. 1. Four sense amplifiers are connected to each of YDEC00 to YDECn0 and YDEC01 to YDECn1. These 4 sense amplifiers are respectively connected to each of IO lines IO00 to IO30 and IO01 to IO31.
Upon reading and writing data, one of YDEC00 to YDECn0 and one of YDEC01 to YDECn1 having the same row address are selected. Both groups of DA00 to DA30 and DA01 to DA31 are activated at the same time. In this manner, 4-bit data in total are input and output simultaneously between ARRAY0 and input-output terminals DQ1 to DQ4 (hereinafter called DQ1 to DQ4) and between ARRAY1 and input-output terminals DQ5 to DQB (hereinafter called DQ5 to DQ8). As a result, 8-bit data in total for the entire chip are input and output between DQ1 to DQ8, and ARRAY0, ARRAY1 via global internal input-output lines RWB1 to RWB8 (hereinafter called RWB1 to RWB8).
A general semiconductor memory device has a function to obtain a proper chip by replacing a defunct cell with a redundant cell having been installed therein in advance, even when one of cells becomes defunct. This replacement is carried out by a replacement address comparing circuit. The replacement address comparing circuit compares a row address signal input externally with a replacement address having been stored internally. When the both show an agreement, the replacement is carried out by selecting a row decoder connected to the redundant memory cell corresponding to the row address signal. In FIGS. 1 and 2, redundancy judging circuits YRED0 and YRED1 (hereinafter called YRED0 and YRED1) are the replacement address comparing circuits and redundant cell row decoders RYDEC0 and RYDEC1 (hereinafter called RYDEC0 and RYDEC1) select the redundant cell.
In the 4-bit configuration product shown in FIG. 1, either ARRAY0 or ARRAY1 is activated, and input and output of data is carried out by using either IO00 to IO30 or IO01 to IO31.
For example, in the case where YDEC00 in ARRAY0 is replaced by using RYEDC1 in ARRAY1, YRED0 and YRED1 compare the row address signal input externally with the respective replacement addresses having been stored. In this case, only YRED1 shows an agreement and RYDEC1 is selected and then DA00 to DA30 is stopped from being activated (YDEC00 is not activated at this time), while DA01 to DA31 is activated instead.
In this manner, data which have been input and output between the sense amplifiers connected to YDEC00 and the outside are input and output between redundant sense amplifiers connected to RYDEC1 and the outside, and the replacement has thus been carried out. It is possible for each of RYDEC0 and RYDEC1 in a 4-bit configuration DRAM to replace an ordinary cell in both ARRAY0 and ARRAY1.
Meanwhile, in an 8-bit configuration DRAM shown in FIG. 2, both memory cell arrays ARRAY0 and ARRAY1 are activated simultaneously, and data input and output is carried out by using both IO00 to IO30 and IO01 to IO31 simultaneously. Therefore, it is impossible to replace YDEC01 to YDECn1 in ARRAY1 with RYDEC0 in ARRAY0 and so is vice versa, since data from a plurality of sense amplifiers conflict on IO00 to IO30 or IO01 to IO31. Therefore, the range where RYDEC0 or RYDEC1 can replace the memory cell is limited to the memory cell array containing each.
As has been described above, even in the same memory cell array structure, the range of defunct bit lines that each redundant bit line can replace differs at depending on an input-output data width.
In order to improve efficiency in designing and in production of varieties of semiconductor memory devices meeting a demand, it is generally carried out that plural varieties are implemented by the same die and the varieties are switched from one to another by bonding wires or metal wiring on an upper layer. A third conventional semiconductor device shown in FIG. 3 is an example of a DRAM comprising this switching function therein.
FIG. 4 is an example of a circuit diagram of redundancy judging circuits YRED0 and YRED1 shown in FIG. 3. In FIG. 4, among fuse elements F0N and F0T which can be cut, only a fuse element F0N is cut when the least significant bit of a replacement address to be stored is 0, while only a fuse element F0T is cut when that is 1. Other fuse elements F1N.multidot.F1T to F(n-1)N F(n-1)T which can be cut are cut exclusively according to the level of each bit of the replacement address. In other words, by appropriately cutting these fuse elements in advance, a row address of a replacement cell can be stored. Meanwhile, complement signals Y0N and Y0T input externally show the least significant bit of a row address. Other complement signals Y1N.multidot.Y1T to Y(n-1)N .multidot.Y(n-1)T are the signals input externally and showing each bit of the row address of each memory cell.
An operation of this circuit will be explained next. Signal RP is normally LOW and becomes HIGH temporarily upon comparison of the replacement address. Therefore, contact 100 is normally HIGH. Upon comparison of the replacement address, if the replacement address having been stored in the fuses and a row address of each memory cell array which is an external address whose most significant bit has been removed are in agreement, contact 100 remains HIGH and becomes LOW if otherwise. As a result, only when the row address input externally agrees with the replacement address, signal YRSEL is output and a corresponding redundant cell becomes activated. Signals YRSEL in FIGS. 1 to 3 have the same suffixes as of memory cell array ARRAY0 or ARRAY1 in which the signals are generated.
FIG. 5 is a circuit diagram showing a configuration of a multiplexer MUX (hereinafter called MUX) installed in the conventional DRAM shown in FIG. 3. In FIG. 5, signal Yn distinguishes ARRAY0 from ARRAY1 in the case of the 4-bit configuration, and here it shows a most significant bit of a row address input externally. The complement signals thereof are shown as YnN and YnT. Being the most significant bit has nothing to do with the nature of the present invention. Signal MDX4 shows a bit configuration, and in the case of 4-bit, it becomes HIGH while Low in 8-bit. Signal MDX4 is configured by a circuit which can select a logic level by using bonding to a pad for example, and this circuit is not explicitly shown in FIG. 5. Furthermore, a signal generating process has nothing to do with the nature of the present invention.
MUX connects RWB1 to RWB8 with DQ1 to DQ8 one to one in the case of an 8-bit configuration, that is, if signal MDX4 is LOW. As a result, an operation which is the same as that by the conventional 8-bit configuration product shown in FIG. 2 can be carried out.
On the other hand, in the case of a 4-bit configuration product, that is, if signal MDX4 is HIGH, MUX connects RWB1 to RWB4 with input-output terminals DQ1 to DQ4 one to one when signal YnT is LOW, that is, when ARRAY0 is being activated. When signal YnT is HIGH, that is, when ARRAY1 is being activated, MUX connects RWB5 to RWB8 with input-output terminals DQ1 to DQ4 one to one.
In this manner, by changing a logic level of signal MDX4, the bit configuration can be changed. Therefore, plural varieties in plural bit configurations can be produced even if the chip design is basically the same.
Locations of defunct cells which occur in a memory cell array are not distributed uniformly, but generally take a biased Poisson distribution. Therefore, even if the total number of redundant cells in a chip is the same, the wider the range of ordinary cells that each redundant cell can replace is, the better the replacement of defunct cells in a biased distribution can be conducted. As a result, a probability of obtaining a proper chip replacing all defunct cells can be improved.
In conventional examples shown in FIGS. 1 and 2, each redundant cell in the 4-bit configuration can replace ordinary cells in an area twice as large as in the 8-bit configuration, and the probability of obtaining a proper chip is thus higher for the 4-bit.
In the conventional example shown in FIG. 3, the array configuration regarding defunct cell replacement is the same in both 4-bit and 8-bit configurations. Therefore, in both cases, only ordinary cells in the same region where the redundant cell exists are selected as in the case of the conventional 8-bit configuration. The probability to obtain a proper chip is thus lower than conventional 4-bit configuration products as shown in FIG.